1. Field of the Invention
The present invention generally relates to the field of fabrication of integrated circuits, and, more particularly, to the chemical mechanical polishing (CMP) of material layers, such as metallization layers, during the various manufacturing stages of an integrated circuit.
2. Description of the Related Art
In the manufacturing of sophisticated integrated circuits, a huge number of semiconductor elements, such as field effect transistors, capacitors and the like, are fabricated on a plurality of chip areas (dies) that are spread across the entire surface of the substrate. Due to the ever-decreasing feature sizes of the individual semiconductor elements, it is necessary to provide the various material layers that are deposited on the entire substrate surface and that exhibit a certain topography corresponding to the underlying layers as uniformly as possible so as to ensure the required quality of subsequent patterning processes, such as photolithography, etching and the like. Recently, chemical mechanical polishing has become a widely used technique to planarize an existing material layer in preparation for the deposition of a subsequent material layer. Chemical mechanical polishing is of particular interest for the formation of so-called metallization layers, that is, layers including recessed portions such as vias and trenches filled with an appropriate metal to form metal lines connecting the individual semiconductor elements. Traditionally, aluminum has been used as the preferred metallization layer, and in sophisticated integrated circuits, as many as twelve metallization layers may have to be provided to obtain the required number of connections between the semiconductor elements. Semiconductor manufacturers are now beginning to replace aluminum with copper—due to the superior characteristics of copper over aluminum with respect to electromigration and conductivity. Through use of copper, the number of metallization layers necessary to provide for the required functionality may be decreased since, in general, copper lines can be formed with a smaller cross-section due to the higher conductivity of copper compared to aluminum. Nevertheless, the planarization of the individual metallization layers remains of great importance. A commonly used technique for forming copper metallization lines is the so-called damascene process in which the vias and trenches are formed in an insulating layer with the copper subsequently being filled into the vias and trenches. Thereafter, excess metal is removed by chemical mechanical polishing after the metal deposition, thereby obtaining planarized metallization layers. Although CMP is successfully used in the semiconductor industry, the process has proven to be complex and difficult to control, especially when a great number of large-diameter substrates are to be treated.
In a CMP process, substrates, such as the wafers bearing the semiconductor elements, are mounted on an appropriately formed carrier, a so-called polishing head, and the carrier is moved relative to the polishing pad while the surface of the wafer is in contact with a polishing pad. During this process, a slurry is supplied to the polishing pad, wherein the slurry contains a chemical compound that reacts with the material or materials of the layer to be planarized by, for example, converting the metal into an oxide, and the reaction product, such as copper oxide, is mechanically removed by abrasives contained in the slurry and the polishing pad. One problem with CMP processes arises from the fact that, at a certain stage of the process, different materials may be present on the layer to be polished at the same time. For example, after removal of the majority of the excess copper, the insulating layer material, for example silicon dioxide, as well as the copper and copper oxide, have to simultaneously be treated chemically and mechanically by the slurry, the polishing pad and the abrasives within the slurry. Usually, the composition of the slurry is selected to show an optimum polishing characteristic for a specified material. In general, the different materials exhibit different removal rates so that, for example, the copper and copper oxide are removed more rapidly than the surrounding insulating material. As a consequence, recessed portions are formed on top of the metal lines compared to the surrounding insulating material. This effect is usually referred to as “dishing.” Moreover, during removal of the excess metal in the presence of the insulating material, the insulating material is also removed, although typically at a reduced removal rate compared to the copper, and thus the thickness of the initially deposited insulating layer is reduced. The reduction of the thickness of the insulating layer is commonly referred to as “erosion.”
Erosion and dishing, however, not only depend on the differences in the materials that comprise the insulating layer and the metal layer, but may also vary across the substrate surface and may even change within a single chip area in correspondence with the pattern that is to be planarized. That is, the removal rate of the metal and the insulating material is determined based upon a variety of factors such as, for example, the type of slurry, the configuration of the polishing pad, structure and type of the polishing head, the amount of the relative movement between the polishing pad and the substrate, the pressure applied to the substrate while moving relatively to the polishing pad, the location on the substrate, the type of feature pattern to be polished, and the uniformity of the underlying insulating layer and of the metal layer, etc.
From the above considerations, it is evident that a plurality of interrelated parameters affect the topography of the finally-obtained metallization layer. Accordingly, a great deal of effort has been made to develop CMP tools and methods to improve the reliability and robustness of CMP processes. For example, in sophisticated CMP tools, the polishing head is configured to provide two or more portions that may exert an adjustable pressure to the substrate, thereby controlling the frictional force and thus the removal rate at the substrate regions corresponding to these different head portions. Moreover, the polishing platen carrying the polishing pad and the polishing head are moved relative to each other in such a way that as uniform a removal rate as possible is obtained across the entire surface area, and so that the lifetime of the polishing pad that gradually wears during operation is maximized. To this end, a so-called pad conditioner is additionally provided in the CMP tool that moves on the polishing pad and reworks the polishing surface so as to maintain similar polishing conditions for as many substrates as possible. The movement of the pad conditioner is controlled in such a manner that the polishing pad is substantially uniformly conditioned while, at the same time, the pad conditioner will not interfere with the movement of the polishing head.
Due to the complexity of CMP processes, it may be necessary to implement two or more process steps, preferably on different polishing platens, to obtain a polishing result that meets the strict requirements in the fabrication of cutting-edge semiconductor devices. For instance, in manufacturing a metallization layer, a minimum cross-section of the individual metal lines has to be established to achieve a desired resistance according to design rules. The resistance of the individual metal lines depends on the type of material, the line length and the cross-section. Although the two former factors do not substantially change during the fabrication process, the cross-section of the metal lines may significantly vary and thus influence the resistance and the quality of the metal lines owing to erosion and dishing created in the involved CMP process. Accordingly, semiconductor designers have to take these variations into account and implement an additional “safety” thickness of the metal lines such that the cross-section of each metal line is reliably within the specified tolerances after polishing operations are finished.
As is apparent from the above considerations, great efforts are being made to improve the yield in the chemical mechanical polishing of substrates while maintaining a high quality standard. Due to the nature of the CMP process, an in situ measurement of the thickness of the layer to be removed and/or of the removal rate is very difficult to predict. In practice, a plurality of dummy substrates are used to condition and/or calibrate the CMP tool before or after a predefined number of product substrates have been processed. Since the processing of dummy wafers is extremely cost-intensive and time-consuming, it has recently been attempted to significantly reduce the number of test runs by implementing suitable control mechanisms to maintain the performance of the CMP process. In general, it would be highly desirable to have a control process in which specific CMP parameters are manipulated on the basis of measurement results of the substrate that has just been processed in order to accurately maintain the final layer thickness and dishing and erosion within the specifications. To accomplish this co-called “run-to-run” control in the production line, at least two conditions have to be satisfied. First, appropriate metrology tools have to be implemented into the production line such that each substrate, having completed the CMP process, is immediately subjected to a measurement, the results of which have to be provided to the CMP tool prior to the CMP process or at least prior to the final stage of the CMP process of the substrate that immediately follows. Second, a model of the CMP process has to be established that reveals appropriate, manipulated variables to obtain the desired polishing results.
The first condition may not be fulfilled without significantly adversely affecting other parameters of the manufacturing process, such as throughput, and thus cost-effectiveness. Accordingly, in practice, a plurality of substrates are subjected to the CMP process until the first measurement result of the initially processed substrate is available. That is, the control loop contains a certain amount of delay that must be taken into consideration when adjusting the process parameters on the basis of the measurement results.
Regarding the second item, a plurality of CMP models have been established to take account for the fact that the manipulated variables are controlled on the basis of aged feedback results. For example, in the proceedings for the AEC/APC VIII Symposium 2001, “A Comparison of R2R Control Algorithms for the CMP with Measurement Delays,” Chamness et. al. disclose the results of a comparison of three CMP models when operated under the condition of a delayed measurement feedback. In this paper, the authors showed that merely a model-predictive run control could avoid any instabilities in the control function when the measurement results are provided with a certain degree of delay to the CMP tool.
In view of this prior art, in general, a predictive model is desired such as the model described in the paper cited above and/or a set of experimental data to extract process variables, such as pressure applied to the substrate, slurry composition, etc., that may be manipulated to obtain the desired output of the CMP process.
Although CMP process control is successfully employed in many semiconductor facilities, from the considerations given so far, it is, however, apparent that a reliable and robust CMP process for sophisticated, integrated circuits involves great efforts in terms of process tools and control operations and it is thus highly desirable to have a simplified yet efficient CMP control process and control system, while also ensuring the required high quality standard of the processed substrates.
The present invention is directed to a method that may solve, or at least reduce, some or all of the aforementioned problems.